The present invention relates to a process for making channels in a substrate, and, more particularly, to a process for making precisely sized channels by segmenting their walls in such a way that the walls disintegrate during the etching step.
In printer heads, such as thermal ink jet print heads, ink is transferred from an ink reservoir through channels to channel orifices or nozzles. Orientation dependent etching (ODE) or anisotropic etching is used to etch the channels in a substrate such as silicon. There are several processes for producing such channels in silicon.
In an orientation dependent etching process of silicon, features are limited to rectangular structures. Alignment to the &lt;110&gt; direction on the {100} silicon plane is critical to good dimensional control. The loss of dimensional control resulting from misalignment of the mask pattern to the &lt;110&gt; direction of the silicon wafer can be determined from equation 1, below: EQU W.sub.F =W.sub.O Cos .THETA.+L.sub.O Sin .THETA.
where
W.sub.F =Final Width Dimension PA0 W.sub.O =Mask Width Dimension PA0 L.sub.O =Mask Length Dimension PA0 .THETA.=Misorientation of the mask to the &lt;110&gt; direction of the silicon wafer.
A stable structure, as defined by the above equation, will be attained if sufficient etch time is allowed.
For an orientation dependent etch process there is also a bath related undercutting dependent on the bath composition and temperature. The etch rate ratio of the {100}:{111} silicon planes will vary depending on composition, concentration and temperature of the etch bath. This etch rate ratio must be known in order to properly design a mask. A typical undercut expected for full through etching of a 500 .mu.m thick (100) surface plance silicon wafer is 5 .mu.m for a 30% KOH--H.sub.2 O etch bath at 95.degree. C.
In a one-step etch process, a single photolithographic and anisotropic etch step is used to form channels, reservoir, and dicing relief structures in a (100) surface place silicon wafer. Referring generally to FIG. 1, the channels 1 and reservoir 3 for a one-step process are shown. The advantages of this process is its simplicity and low cost. However, the one-step process requires long etch times, which drive the channel structures to be completely terminated by {111} crystal planes in the substrate. Therefore, the process is sensitive to misorientation between the lithographically defined etch mask (e.g. Si.sub.3 N.sub.4) and the &lt;110&gt; crystal direction on the (100) surface plane direction as well as the misorientation of the wafer (100) surface plane. The anisotropic etching process is driven to completion because the etch proceeds horizontally along the channels as well as vertically into the surface. Thus, the time required for a given structure to completely terminate depends on the longest dimension of the channel feature. The one-step process is advantageous if the tolerances of the channel dimensions can be tightly controlled. Using the mask shown in FIG. 1, channel size uniformity is .+-.1 .mu.m, 3.sigma..
In a two-step terminated process, two photolithographic etching steps are performed before the orientation dependent etching steps. Referring to FIG. 2, the two-step terminated process is shown generally. In the first etching step, the substrate is exposed to an anisotropic etchant through a mask which is typically made of Si.sub.3 N.sub.4 (appears as a solid line in FIG. 2). After the long etch time, structures are etched through the substrate (i.e. fill hole and reservoir 7), the Si.sub.3 N.sub.4 mask is chemically stripped, leaving a second etch mask, which is typically SiO.sub.2 (appears as a dashed line in FIG. 2). The SiO.sub.2 etch mask allows separated channels 5 to be anisotropically etched adjacent to the reservoir 7. The depth of the channels 5 are quite small as compared to the thickness of the wafer. For example, the depth of the channels 5 would be on the order of 40 .mu.m while the wafer will have a thickness of 500 .mu.m. Thus, the second etch time is much smaller (approximately 90% smaller) than the first etch. The short second etch is sufficient to allow this anisotropic etch to terminate in a V shape. However, misorientation between the channel pattern and the &lt;110&gt; direction is not completely resolved and a stable structure is not achieved due to the very short etch time. In typical specifications for semiconductor wafers, up to a 1.0.degree. discrepancy in the alignment of the &lt;110&gt; silicon crystal plane and the wafer flat is common. The two-step terminated process enables an inherently tighter channel dimensional control, but has increased process complexity and cost.
In a two-step unterminated process, the channels are connected to the reservoir in the second etching step. To have an appropriate connection, the timing of the second etching step has to be very exact. Also, the etch aspect ratio is unfavorable since lateral etching is faster than depth etching. For example, 6 mils of channel length is lost in etching approximately 1.5 mils deep. The lateral etch rate is also variable which leads to uniformity problems in channel length dimensions.
Examples of methods for etching channels are shown in U.S. Pat. Nos. 4,915,718 and 4,600,934. The '718 patent relates to a two-step etching process where a channel is started in the first etching step with a nozzle area substantially masked. In the second etching step, the masking is removed and the nozzle is etched with the channel forming a shallow connection between the channel and a reservoir.
The '934 patent relates to a method for undercut anisotropic etching of semiconductor material. In this method, etching is performed on the (110) face of the substrate at angles as close to the &lt;111&gt; direction as possible so that oriented side edges will be undercut from the sides.
In the aforementioned methods for fabricating channels and reservoirs in substrates for thermal ink-jet printheads and other devices, errors occur due to pattern misalignment to the &lt;110&gt; direction of the substrate. For instance, a typical channel is 50 .mu.m by 500 .mu.m having its lengthwise axis perpendicular to the &lt;110&gt; direction. If the &lt;110&gt; direction is misoriented by 0.2.degree. with respect to the lengthwise mask channel axis, then the channel will increase in width by 1.57 .mu.m to 51.57 .mu.m, if given sufficient etching time. Such an increase in width does not occur when the &lt;110&gt; direction is perfectly oriented. The standard manufacturing tolerance for the orientation of the &lt;110&gt; direction in a wafer and the substrate flat is .+-.1.0.degree., so an error such as this is quite common.
In view of the methods described above, there is a need for an improved method of forming channels in substrates having precise dimensions. There is also a need for a method that is simpler and economically efficient as compared to previous methods.